https://cybertoolchain.io/tools/capstone New releases and features in Capstone, tracked by The Cyber Toolchain. en Mon, 21 Sep 2026 17:53:59 GMT https://github.com/capstone-engine/capstone/releases/tag/6.0.0-Alpha11 https://github.com/capstone-engine/capstone/releases/tag/6.0.0-Alpha11 Mon, 21 Sep 2026 17:53:59 GMT Capstone 6.0.0-Alpha11 adds CS_MODE_X86_AMD/INTEL x86 vendor modes, CS_MODE_XTENSA_ESP32S3 gating, and PowerPC mcrxr instruction support.⁠︀︄︇︀︅︉︀︅︀︀︃︀︀︅︅︀︅︊︀︄︆︀︃︄⁠ • Adds `CS_MODE_X86_AMD` and `CS_MODE_X86_INTEL` mode flags for x86 to enable vendor-specific disassembly behavior (currently affecting `JO`/`JNO` operand size in 64-bit mode).⁠︀︄︇︀︅︉︀︅︀︀︃︀︀︅︅︀︅︊︀︄︆︀︃︄⁠ • Gates Xtensa ESP32-S3 and HIFI3 instructions behind the new `CS_MODE_XTENSA_ESP32S3` mode flag to avoid unintended decode on other Xtensa targets. Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/capstone-engine/capstone/releases/tag/6.0.0-Alpha10 https://github.com/capstone-engine/capstone/releases/tag/6.0.0-Alpha10 Tue, 21 Jul 2026 17:12:50 GMT Capstone 6.0.0-Alpha10 adds AArch64 explicit wide-immediate printing, RISC-V FP rounding mode details, and a RISC-V v5 compat macro. • Adds `CS_OPT_SYNTAX_AARCH64_EXPLICIT_WIDE_IMM` flag to print `MOVN`/`MOVZ` instructions in explicit shifted form instead of `MOV` aliases. • RISC-V instruction details now expose the FP rounding mode via `cs_riscv.rounding_mode`. • New `CAPSTONE_RISCV_COMPAT_HEADER` define restores the `CS_MODE_RISCVC` alias for codebases targeting the v5 API. • Adds ColdFire EMAC_B dual-accumulator MAC support to the M68K module. Breaking changes: • Alpha architecture enum names are renamed from `Alpha_`-prefixed mixed-case to `ALPHA_`-prefixed uppercase (e.g., `Alpha_REG_Foo` → `ALPHA_REG_FOO`); any code referencing the old names will fail to compile. • `CS_MODE_RISCVC` was renamed to `CS_MODE_RISCV_C`; builds not using the new `CAPSTONE_RISCV_COMPAT_HEADER` workaround will break. • `aarch64_op_mem.disp` changed from `int32_t` to `int64_t`; code that stores or passes this field as a 32-bit integer may break. Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/aquynh/capstone/releases/tag/6.0.0-Alpha8 https://github.com/aquynh/capstone/releases/tag/6.0.0-Alpha8 Sat, 23 May 2026 19:23:25 GMT Capstone 6.0.0-Alpha8 adds ColdFire ISA, RS08/HCS12X, RISC-V reg_access, x86 MOVSXD support, and faster x86 LUT decoding. • Adds ColdFire ISA support to the M68K architecture (sponsored by RizinOrg). • Extends M680X architecture support to the RS08 and HCS12X instruction sets. • Adds `reg_access` field to RISC-V instruction details, exposing per-operand read/write access information. • Adds decoding support for x86 `MOVSXD` instructions (r32/r16 forms). • Introduces a `+noaliascompressed` option to selectively disable aliasing for compressed RISC-V instructions only. • Speeds up x86 decoding via lookup tables, enabling faster disassembly throughput. • Adds RISC-V Ventana vendor to the public API. Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/aquynh/capstone/releases/tag/5.0.8 https://github.com/aquynh/capstone/releases/tag/5.0.8 Sat, 23 May 2026 18:01:13 GMT Capstone 5.0.8 adds x86 MOVSXD support, LUT-based x86 speedup, and RTLD_DEEPBIND isolation for Python on Linux. • Adds support for decoding x86 `MOVSXD` instructions. • Speeds up x86 decoding by switching to lookup tables (LUTs), unlocking faster disassembly pipelines. • Python bindings on Linux now load `libcapstone.so` with `RTLD_DEEPBIND`, isolating symbol scope and enabling safe use alongside a second Capstone version in the same process. Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/aquynh/capstone/releases/tag/6.0.0-Alpha7 https://github.com/aquynh/capstone/releases/tag/6.0.0-Alpha7 Mon, 16 Feb 2026 13:18:56 GMT Capstone 6.0.0-Alpha7 ships a fully rebuilt RISC-V module via Auto-Sync/LLVM and adds 32-bit architecture build support. • Rebuilt RISC-V disassembly module via Auto-Sync from LLVM, bringing the architecture up to date with active RISC-V development. • Supports building and testing on 32-bit architectures, including i686 Windows. Breaking changes: • x86-64: ES/CS/SS/DS segment overrides are now ignored in x64 mode to match CPU behavior, changing decoding results for instructions that previously decoded those overrides. Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/aquynh/capstone/releases/tag/6.0.0-Alpha6 https://github.com/aquynh/capstone/releases/tag/6.0.0-Alpha6 Tue, 13 Jan 2026 15:53:31 GMT Capstone 6.0.0-Alpha6 adds M68K displacement size fields, broader x86 register semantics, and free-threaded CPython 3.14 support. • Adds displacement size fields to the M68K disassembler, exposing richer operand detail for M68K instructions. • Expands x86 read/written register tracking to cover call, interrupt, interrupt-return, string, loop, conditional jump, unconditional jump, system call, enter/leave, procedure return, and cmpxchg instructions. • Supports Python 3.14 free-threaded (no-GIL) CPython builds in the Python binding. • Handles previously ignored operands in M68K, including displacement and suppressed register details. • Builds static Capstone libraries with PIC enabled, enabling use in shared-library contexts. Breaking changes: • The `csh` and `value` arguments of `cs_option` are now of type `uintptr_t` instead of their previous types, which may require source-level changes in code passing these arguments. • Alpha architecture immediate operands are now typed as `int64_t`; code reading these fields as a narrower or unsigned type will need updating. Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/aquynh/capstone/releases/tag/6.0.0-Alpha5 https://github.com/aquynh/capstone/releases/tag/6.0.0-Alpha5 Tue, 05 Aug 2025 12:11:20 GMT Capstone 6.0.0-Alpha5 adds Apple AArch64 proprietary instruction support, SPARC updated to LLVM-18, and Python ABI3 wheels. • Adds support for Apple's proprietary AArch64 instructions (as documented by the Asahi Linux project). • Updates the SPARC module to LLVM-18 via Auto-Sync. • Marks instructions that decode successfully but are otherwise invalid with a new SoftFail flag. • Python bindings now ship as ABI3 wheels, enabling compatibility across Python versions without per-version builds. • Python bindings now include a Windows ARM64 build. • Adds jump group classification for the generic LoongArch `jirl` instruction. • Implements `cs_regs_access` for the Alpha architecture. • Uses `cs_ac_type` uniformly for operand access mode across all architectures, and `cs_xtensa_op_type` for Xtensa operand types. • Prints immediate-only memory operands for AArch64. • Enables generation of legacy MC tests for the fuzzer. Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/aquynh/capstone/releases/tag/6.0.0-Alpha4 https://github.com/aquynh/capstone/releases/tag/6.0.0-Alpha4 Mon, 14 Apr 2025 11:01:49 GMT Capstone 6.0.0-Alpha4 adds MIPS alias mapping, TMS320C64x little-endian support, PPC BH field decoding, and call-group tagging for AArch64 system calls. • Adds instruction alias mapping for MIPS architecture, enabling lookup by both instruction ID and alias ID. • Adds little-endian disassembly support for the TMS320C64x architecture. • Adds call group classification to AArch64 `svc`, `smc`, and `hvc` instructions for control-flow analysis. • Adds decoding and stringification of the BH (Branch Hint) field in PowerPC instruction details. • Enhances shift value and shift type information in shift instructions across architectures. • Produces PDB debug symbol files when building Capstone on Windows. Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/aquynh/capstone/releases/tag/5.0.6 https://github.com/aquynh/capstone/releases/tag/5.0.6 Sun, 23 Mar 2025 15:49:39 GMT Capstone 5.0.6 adds little-endian support for the TMS320C64x DSP architecture. • Supports little-endian mode for the TMS320C64x DSP architecture. Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/aquynh/capstone/releases/tag/6.0.0-Alpha3 https://github.com/aquynh/capstone/releases/tag/6.0.0-Alpha3 Tue, 28 Jan 2025 17:04:33 GMT Capstone 6.0.0-Alpha3 adds ARC architecture support, TriCore 1.8, BPF RFC 9669 updates, PPC LLVM 18 instructions, and deb/rpm packaging. • New ARC architecture disassembly module. • BPF module updated to RFC 9669 with additional opcode sources. • Adds TriCore 1.8 instruction support. • PPC module updated to LLVM 18, adding new instructions. • EVM module updated with new opcodes. • Expanded Python wheels covering more architecture and OS combinations. • Native `deb` and `rpm` packages now available via CPack. • arm64 and sysz compatibility layer added to Python bindings. • LoongArch gains `CS_OPT_SYNTAX_NO_DOLLAR` syntax option support. • x86 read/write register tracking improved for transfer instructions. Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/capstone-engine/capstone/blob/next/ChangeLog https://github.com/capstone-engine/capstone/blob/next/ChangeLog Sun, 24 Nov 2024 00:00:00 GMT Capstone 6.0.0-alpha2 adds ARM/AArch64 compatibility macros for CC/VAS enums and Tricore EA calculation • Adds ARM and AArch64 compatibility macros for the CC/VAS enums Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/aquynh/capstone/releases/tag/6.0.0-Alpha1 https://github.com/aquynh/capstone/releases/tag/6.0.0-Alpha1 Mon, 30 Sep 2024 15:19:26 GMT Capstone 6.0 adds LoongArch, HPPA, and Alpha architectures, LLVM 18 updates, NanoMips, instruction aliases, and Auto-Sync. • Adds LoongArch, HPPA (PA-RISC), and Alpha architecture disassembly support. • Updates AArch64, SystemZ, and Mips disassemblers to LLVM 18. • Updates ARM and PPC disassemblers to LLVM 16. • Adds NanoMips extension support. • Adds exotic PPC PairedSingle extension support. • Adds instruction alias support across architectures. • Adds RISC-V operand access information (read/write flags per operand). • Exposes instruction formats for PPC, SystemZ, and LoongArch. • Introduces Auto-Sync mechanism enabling easier architecture module updates and additions. • Adds dynamic architecture registration API. • Adds eBPF bswap16/32/64 instruction support. • Adds big-endian mode for the Alpha architecture. • Adds several API improvements to the ARM, AArch64, and PPC modules. Breaking changes: • `ARM64` is renamed to `AArch64` everywhere (a compatibility header is provided, but code referencing `ARM64` names may break without it). • `SysZ` is renamed to `SystemZ` everywhere (a compatibility header is provided, but code referencing `SysZ` names may break without it). • The PPC, ARM, and AArch64 APIs have breaking changes to enumeration values and structs — existing code using these modules must be updated per the v6 release guide. Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/aquynh/capstone/releases/tag/5.0.2 https://github.com/aquynh/capstone/releases/tag/5.0.2 Mon, 12 Aug 2024 07:42:13 GMT Capstone 5.0.2 adds AArch64 meta-programming macros to ease the ARM64 name-change transition. • Adds meta-programming macros (`CS_aarch64`) in `capstone.h` to smooth the ARM64→AArch64 API rename, including a parameter-free `CS_aarch64` macro variant. Breaking changes: • The constant value of `CS_OP_MEM` is reverted to its v5.0.1 value — code that relied on the value introduced between 5.0.1 and 5.0.2 must be updated. Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/aquynh/capstone/releases/tag/5.0.1 https://github.com/aquynh/capstone/releases/tag/5.0.1 Wed, 23 Aug 2023 01:58:13 GMT Capstone 5.0.1 adds Python bindings for WASM and SH architectures. • `Add Python bindings for WASM` enables disassembly capabilities for the WebAssembly architecture in the Capstone Python library • `Add Python bindings for SH` extends the Python API to support disassembling SuperH (SH) instructions Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/aquynh/capstone/releases/tag/5.0 https://github.com/aquynh/capstone/releases/tag/5.0 Wed, 05 Jul 2023 14:58:41 GMT Capstone 5.0 adds support for the `repz` prefix on X86 ret instructions and changes Tricore operand syntax • Adds `repz` prefix support on X86 `ret` instructions to correctly decode this specific sequence. • Changes Tricore register output format to use Intel register syntax, and adds a `#` prefix to Tricore immediate operands. Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/capstone-engine/capstone/blob/next/ChangeLog https://github.com/capstone-engine/capstone/blob/next/ChangeLog Wed, 05 Jul 2023 00:00:00 GMT Capstone 5.0 adds repz prefix support for X86 RET and Tricore Intel syntax • Support `repz` prefix on X86 RET instructions for more accurate decoding of specific call-return patterns. • Add `#` prefix to Tricore immediate operands in disassembled output. Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone https://github.com/capstone-engine/capstone/blob/next/ChangeLog https://github.com/capstone-engine/capstone/blob/next/ChangeLog Sun, 27 Feb 2022 00:00:00 GMT Capstone 5.0 introduces BPF, RISC-V, and WASM architecture support along with Swift bindings. • Adds `BPF` architecture disassembly support • Adds `RISCV` architecture disassembly support • Adds `WASM` architecture disassembly support • Adds Swift language binding for the library Full history on Cyber Toolchain: https://cybertoolchain.io/tools/capstone