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Capstone

5.0.8 open-source

Capstone is a disassembly framework supporting multiple hardware architectures, designed for binary analysis and reversing in the security community.

Summary

Capstone is an open-source disassembly framework used as a library for binary analysis and reverse engineering, distributed under the BSD license. It covers a wide range of instruction sets — ARMARMA family of RISC processor architectures designed by Arm Holdings and licensed to chip makers worldwide; tools target it to run natively on mobile, embedded, and increasingly server and desktop hardware., x86, MIPSMIPSA RISC processor architecture originally developed at Stanford and commercialized by MIPS Technologies, widely used in embedded and network devices; cyber tools target it to analyze or exploit routers, cameras, and similar hardware., PowerPC, RISC-V, M68K, WebAssemblyWebAssemblyA binary instruction format that runs in browsers and server runtimes at near-native speed, letting developers compile C, Rust, or other languages into a portable, sandboxed module any compliant host can execute., and dozens more — through a single architecture-neutral C API, with bindings for languages including Python, Rust, Go, and Java, so it drops into tools written in most common stacks. It's aimed at malware analysts and reverse engineers building or extending disassembly tooling rather than at end users running a standalone application, and its thread-safe, embeddable design suits use inside firmware or kernel-level analysis tools as well as desktop ones. First committed in 2013, it remains active with 389 contributors, 140 commits and 11 releases in the past year, and a release only 31 days ago.

Capstone is a disassembly framework supporting multiple hardware architectures, designed for binary analysis and reversing in the security community.

How Capstone helps

What instruction set is this unfamiliar binary blob actually written in?

decodes the byte stream against any of its supported architectures — ARM, x86, MIPS, PowerPC, RISC-V, M68K, WebAssembly, and dozens more — through one architecture-neutral API, so the same calling code identifies instructions regardless of the target ISA

Which registers does this instruction actually read and write?

returns per-operand access details (implicit and explicit registers touched) for the decoded instruction, giving the semantics needed for taint tracking or data-flow analysis rather than just a mnemonic

Can I disassemble untrusted or malware-crafted code without one thread's analysis corrupting another's?

is built thread-safe, so multiple disassembly calls can run concurrently inside the same process without shared state clobbering results

Will this instruction stream trip up my analysis tool the way it would a real CPU?

is tuned to handle the tricks x86 malware uses to confuse disassemblers, and flags instructions that decode but are structurally invalid with a distinct fail state rather than silently mis-parsing them

How do I add disassembly to a tool written in Python, Rust, Go, or Java instead of C?

exposes the same C engine through bindings in those languages and others, so the tool calls into one library rather than re-implementing decoding per language

Can I embed disassembly inside firmware or kernel-level tooling, not just a desktop app?

is designed as a lightweight, embeddable library rather than a standalone application, so it drops into constrained runtime environments like kernels or firmware analysis tools

all 15 features, with the evidence for each →

Languages

Not documented

Features

15 capabilities · 5 backed by code, an API document or a real run

Built from Capstone's releases, docs, README and our own runs. “Seen” marks the month we first spotted a release the vendor didn't date. Group names and tags are our labels.

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What Capstone offers you

  • Command-line interface3
  • Python scripting support1
  • Scripting API1
  • Scripting language support1
All capabilities 15 capabilities
Multi-architecture disassembly shipped Decodes and disassembles instructions across multiple CPU architectures, including AArch64, RISC-V, M68K, Alpha, and others, exposing per-instruction details such as operands, memory displacements, and FP rounding modes. 83 releases · 6 other sources · first seen Mar 2014

release 83 total

  • Adds support for the mcrxr instruction in the PowerPC disassembly module. announced · Sep 2026 · source · release history
  • Gates Xtensa ESP32-S3 and HIFI3 instructions behind the new CS_MODE_XTENSA_ESP32S3 mode flag to avoid unintended decode on other Xtensa targets. 6.0.0-Alpha11 · Sep 2026 · source · release history
  • New mcrxr instruction support in PowerPC 6.0.0-Alpha11 · Sep 2026 · source · release history
  • RISC-V instruction details now expose the FP rounding mode via cs_riscv.rounding_mode. 6.0.0-Alpha10 · Jul 2026 · source · release history
  • aarch64_op_mem.disp changed from int32_t to int64_t; code that stores or passes this field as a 32-bit integer may break. 6.0.0-Alpha10 · Jul 2026 · source · release history
  • Alpha architecture enum names are renamed from Alpha_-prefixed mixed-case to ALPHA_-prefixed uppercase (e.g., Alpha_REG_Foo → ALPHA_REG_FOO); any code referencing the old names will fail to compile. 6.0.0-Alpha10 · Jul 2026 · source · release history

docs

  • Multi-architecture disassembly framework for binary analysis and reversing, supporting ARM, x86, RISC-V, MIPS, and many more architectures.

example

  • Decode ESP32-S3 specific instructions only when the target platform is enabled. cshandle = cs_open(CS_ARCH_XTENSA, CS_MODE_LITTLE_ENDIAN | CS_MODE_XTENSA_ESP32S3) 6.0.0-Alpha11 · Sep 2026 · source
  • Disassemble Xtensa firmware built for the ESP32-S3 to expose ESP32-S3 and HIFI3 instructions that are hidden in the default mode. cs = Cs(CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32S3) for i in cs.disasm(firmware_bytes, 0x40000000): print(i.mnemonic, i.op_str) announced · Sep 2026 · source
  • Disassemble Xtensa firmware built for the ESP32-S3 to correctly decode ESP32-S3- and HIFI3-specific instructions that are otherwise gated off. csh = Cs(CS_ARCH_XTENSA, CS_MODE_XTENSA_ESP32S3) for insn in csh.disasm(firmware_bytes, 0x40000000): print('0x%x:\t%s\t%s' % (insn.address, insn.mnemonic, insn.op_str)) 6.0.0-Alpha11 · Sep 2026 · source
  • Disassemble ARMv8 binary using the new cstool mode cstool -d armv8 <binary.bin> 4.0.2 · May 2020 · source
  • Specify MIPS32R6 hardware mode explicitly for newer MIPS targets cs_open(CS_ARCH_MIPS, CS_MODE_MIPS32R6, &handle); 3.0 · Nov 2014 · source
Output formatting verified Applies a specified .clang-format configuration to format generated output files. 6 releases · 4 other sources · first seen May 2020

Also counts toward: Command-line interface

release

  • CS_MODE_X86_AMD and CS_MODE_X86_INTEL flags to toggle alternative disassembly for x86 JO/JNO operands 6.0.0-Alpha11 · Sep 2026 · source · release history
  • Adds CS_MODE_X86_AMD and CS_MODE_X86_INTEL mode flags for x86 to enable vendor-specific disassembly behavior (currently affecting JO/JNO operand size in 64-bit mode).⁠︀︄︇︀︅︉︀︅︀︀︃︀︀︅︅︀︅︊︀︄︆︀︃︄⁠ 6.0.0-Alpha11 · Sep 2026 · source · release history
  • Adds CS_OPT_SYNTAX_AARCH64_EXPLICIT_WIDE_IMM flag to print shifted MOVN and MOVZ instructions in their explicit forms instead of using the equivalent MOV aliases. 6.0.0-Alpha10 · Jul 2026 · source · release history
  • Python bindings on Linux now load libcapstone.so with RTLD_DEEPBIND, isolating symbol scope and enabling safe use alongside a second Capstone version in the same process. 5.0.8 · May 2026 · source · release history
  • Supports Python 3.14 free-threaded (no-GIL) CPython builds in the Python binding. 6.0.0-Alpha6 · Jan 2026 · source · release history
  • Configures cstool to print instruction IDs via new metadata output 4.0.2 · May 2020 · source · release history

command line

example

  • Disassemble x86 jump instructions using AMD syntax rules instead of the default Intel-style. cshandle = cs_open(CS_ARCH_X86, CS_MODE_64 | CS_MODE_X86_AMD) 6.0.0-Alpha11 · Sep 2026 · source
  • Disassemble 64-bit x86 code using Intel vendor semantics so that JO/JNO operands are decoded according to Intel conventions. csh = Cs(CS_ARCH_X86, CS_MODE_64 | CS_MODE_X86_INTEL) for insn in csh.disasm(code, 0x1000): print('0x%x:\t%s\t%s' % (insn.address, insn.mnemonic, insn.op_str)) 6.0.0-Alpha11 · Sep 2026 · source
  • Disassemble 64-bit x86 code using AMD-style JO/JNO operand notation instead of the default representation. cs = Cs(CS_ARCH_X86, CS_MODE_64 | CS_MODE_X86_AMD) for i in cs.disasm(code, 0x1000): print(i.mnemonic, i.op_str) announced · Sep 2026 · source
Cross-language bindings shipped Provides language bindings for scripting and development environments such as PowerShell and VB6. 9 releases · 1 other source · first seen Dec 2018

Also counts toward: Python scripting support, Scripting API, Scripting language support

release 9 total

  • Python bindings now include a Windows ARM64 build. 6.0.0-Alpha5 · Aug 2025 · source · release history
  • Python bindings now ship as ABI3 wheels, enabling compatibility across Python versions without per-version builds. 6.0.0-Alpha5 · Aug 2025 · source · release history
  • arm64 and sysz compatibility layer added to Python bindings. 6.0.0-Alpha3 · Jan 2025 · source · release history
  • Expanded Python wheels covering more architecture and OS combinations. 6.0.0-Alpha3 · Jan 2025 · source · release history
  • Add Python bindings for WASM enables disassembly capabilities for the WebAssembly architecture in the Capstone Python library 5.0.1 · Aug 2023 · source · release history
  • Adds Swift language binding for the library 5.0.0-rc1 · Feb 2022 · source · release history

example

  • Access skipdata settings in Python bindings # Access skipdata mnemonic mnemonic = cs.skipdata_mnem # Set custom callback cs.skipdata_callback = my_callback_fn 4.0.1 · Jan 2019 · source
RISC-V v5/v6 API compatibility verified Provides a compatibility mechanism (--riscv-compat flag and CAPSTONE_RISCV_COMPAT_HEADER define) that lets codebases build against both Capstone v5 and v6 RISC-V headers without source changes. 6 releases · 2 other sources · first seen Aug 2024

Also counts toward: Command-line interface

release

  • CS_MODE_RISCVC was renamed to CS_MODE_RISCV_C; builds not using the new CAPSTONE_RISCV_COMPAT_HEADER workaround will break. 6.0.0-Alpha10 · Jul 2026 · source · release history
  • New CAPSTONE_RISCV_COMPAT_HEADER define restores the CS_MODE_RISCVC alias for codebases targeting the v5 API. 6.0.0-Alpha10 · Jul 2026 · source · release history
  • CS_MODE_RISCVC is renamed to CS_MODE_RISCV_C; builds against a v5 code base using the old name will break unless CAPSTONE_RISCV_COMPAT_HEADER is defined. 6.0.0-Alpha10 · Jul 2026 · source · release history
  • Adds ARM and AArch64 compatibility macros for the CC/VAS enums 6.0.0-alpha2 · Nov 2024 · source · release history
  • Adds meta-programming macros (CS_aarch64) in capstone.h to smooth the ARM64→AArch64 API rename, including a parameter-free CS_aarch64 macro variant. 5.0.2 · Aug 2024 · source · release history
  • The constant value of CS_OP_MEM is reverted to its v5.0.1 value — code that relied on the value introduced between 5.0.1 and 5.0.2 must be updated. 5.0.2 · Aug 2024 · source · release history

command line

  • --riscv-compat — Patch the RISC-V compatibility macros into the RISC-V header 6.0.0-Alpha10 · Jul 2026 · command-line history

example

  • Maintain a single codebase that builds against both Capstone v5 and v6 RISC-V headers without renaming CS_MODE_RISCVC. #define CAPSTONE_RISCV_COMPAT_HEADER #include <capstone/capstone.h> // CS_MODE_RISCVC now works as an alias for CS_MODE_RISCV_C cs_open(CS_ARCH_RISCV, CS_MODE_RISCV32 | CS_MODE_RISCVC, &handle); 6.0.0-Alpha10 · Jul 2026 · source
Memory and size optimization shipped Reduces memory usage and binary size through diet mode and general code improvements. 4 releases · 1 other source · first seen Mar 2014

release

  • cstool gains -s flag to enable skipdata mode 4.0.1 · Jan 2019 · source · release history
  • Improves memory usage by 40% and reduces binary sizes by at least 30% 2.1 · Mar 2014 · source · release history
  • Adds diet mode to reduce binary size by ~40% at the cost of non-critical data fields 2.1 · Mar 2014 · source · release history
  • Extends cs_support() with new query type CS_SUPPORT_DIET and error code CS_ERR_DIET for diet status queries 2.1 · Mar 2014 · source · release history

example

  • Enable skipdata mode in cstool via CLI cstool -s <architecture> <bytes> 4.0.1 · Jan 2019 · source
Register access tracking shipped Exposes per-operand read and write register access information within instruction details to support data-flow analysis. 2 releases · 1 other source · first seen Jan 2026

release

  • Adds reg_access field to RISC-V instruction details, exposing per-operand read/write access information. 6.0.0-Alpha8 · May 2026 · source · release history
  • Expands x86 read/written register tracking to cover call, interrupt, interrupt-return, string, loop, conditional jump, unconditional jump, system call, enter/leave, procedure return, and cmpxchg instructions. 6.0.0-Alpha6 · Jan 2026 · source · release history

example

  • Inspect read/write register access per operand when disassembling RISC-V — useful for taint tracking or data-flow analysis. import capstone md = capstone.Cs(capstone.CS_ARCH_RISCV, capstone.CS_MODE_RISCV64) md.detail = True for insn in md.disasm(b'\x33\x05\xa6\x00', 0x1000): # add a0, a2, a0 for op in insn.operands:… 6.0.0-Alpha8 · May 2026 · source
Disassembly performance optimization shipped Accelerates instruction decoding through implementation optimizations such as lookup tables. 2 releases · first seen May 2026

release

  • Speeds up x86 decoding by switching to lookup tables (LUTs), unlocking faster disassembly pipelines. 5.0.8 · May 2026 · source · release history
  • Speeds up x86 decoding via lookup tables, enabling faster disassembly throughput. 6.0.0-Alpha8 · May 2026 · source · release history
Bulk instruction decode and test mode verified Optionally decodes and tests all instructions in a text segment together in a single pass, enabling correct handling of instructions that depend on each other. 1 release · 1 other source · first seen Mar 2017

Also counts toward: Command-line interface

release

command line

  • -u — If set, all instructions of a text segment will decoded and tested at once. Should be set, if instructions depend on each other. 6.0.0-Alpha1 · Sep 2024 · command-line history
Code generation and translation output verified Writes generated or translated files for a target architecture to the arch/<ARCH>/ directory. 1 release · 1 other source · first seen Jul 2023

release

  • Changes Tricore register output format to use Intel register syntax, and adds a # prefix to Tricore immediate operands. 5.0 · Jul 2023 · source · release history

command line

  • -w — Write generated/translated files to arch/<ARCH>/ 6.0.0-Alpha1 · Sep 2024 · command-line history
Dynamic architecture registration and module updates shipped Provides APIs to register architectures dynamically at runtime and mechanisms to facilitate easier updates and addition of architecture modules. 2 releases · first seen Sep 2024

release

  • Adds dynamic architecture registration API. 6.0.0-Alpha1 · Sep 2024 · source · release history
  • Introduces Auto-Sync mechanism enabling easier architecture module updates and additions. 6.0.0-Alpha1 · Sep 2024 · source · release history
Logging verbosity control verified Allows the user to adjust the verbosity level of log messages produced during tool execution. 1 release · 1 other source · first seen Jan 2019

release

command line

Iterative disassembly support shipped Provides APIs to iterate over disassembled instructions one by one rather than in bulk. 1 release · 1 other source · first seen Nov 2014

release

  • Adds cs_disasm_iter API for iterative disassembly iteration 3.0 · Nov 2014 · source · release history

example

  • Iterate over disassembled instructions one by one using the new API cs_disasm_iter(csh, &code, &code_len, &addr, &insn); 3.0 · Nov 2014 · source
Debug symbol generation shipped Generates platform-specific debug information files to aid in development and troubleshooting. 1 release · first seen Apr 2025

release

  • Produces PDB debug symbol files when building Capstone on Windows. 6.0.0-Alpha4 · Apr 2025 · source · release history
Distribution packaging support shipped Provides native packages for specific operating system distribution ecosystems to facilitate installation. 1 release · first seen Jan 2025

release

  • Native deb and rpm packages now available via CPack. 6.0.0-Alpha3 · Jan 2025 · source · release history
Runtime environment compatibility shipped Extends library execution support to specialized operating system modes and environments, such as Windows kernel-mode drivers. 1 release · first seen May 2020

release

  • Adds cs engine support for Windows kernel-mode driver in the core library 4.0.2 · May 2020 · source · release history

Lines in monospace are the tool's own words: help text parsed from its source, or an endpoint from its API document. Under release, a line is our summary of a dated release. Under docs, it is quoted from the tool's own documentation or website. Each links back to the source it came from.

Score card

  1. Shipping velocity releases a month, last 12 months
  2. Documentation quality release-notes rubric, 0–100
  3. Breaking-change discipline how rarely a release breaks users, and notice given
  4. Maintenance risk quiet time against its own cadence, maintainers
  5. Innovation & surface new capabilities, API and MCP surface
  6. Community health
  7. Contributor trend distinct committers, this year against last
  8. Maintainer concentration bus factor now against a year ago
  9. Issue backlog trend issues closed per issue opened, 12 months
  10. Responsiveness median time to a maintainer’s first reply

Nine scores for Capstone, each built from the releases, notes and API history this site tracks — and, on Researcher and Business, where it stands among every measured tool in its category and how that has moved.

Score cards are part of every paid plan.

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Each score is 0–100 on a published rubric, derived from data this site already shows. A dimension we cannot measure says so — it is never scored 0 and never enters a rank.

How this is scored
  • Shipping velocity — releases a month over the last 12 months, on a log scale where 16 a month scores 100. Needs 3 releases in the window.
  • Documentation quality — the release-notes rubric published on the analytics page, unchanged.
  • Breaking-change discipline — the share of releases carrying a breaking change (none scores 100, half or more scores 0). Only projects that label breaking changes are measured: a clean record cannot be told from an unlabelled one.
  • Maintenance risk — quiet time measured against the tool's own release cadence (quiet longer than 90 days and three typical gaps scores 0), plus the number of active maintainers and whether contributors are growing, where known. Higher is lower risk.
  • Innovation & surface — new capabilities in the feature ledger this year, API and MCP operations added, and the share of commits that are features: the mean of whichever we hold.
  • Community health (open-source tools only) — each is a direction, not a size: contributors this year against last, the bus factor now against a year ago, and issues closed per issue opened, where steady scores 50, doubled 100 and halved 0; plus the median time to a maintainer's first reply (an hour scores about 100, a month or more 0). A commercial card has no repository and carries none of the four.
  • Documented delivery (commercial tools) — when a vendor's documented new capabilities have slowed against its own baseline, that counts against the overall standing as heavily as two low dimensions. Steady delivery, or too little history to judge, leaves the standing alone; it is never a sixth score.
  • Open-source tools are scored on repository signals; commercial tools on their published changelog. Ranks compare tools within one category and one profile and need at least five measured peers; the overall standing needs three ranked dimensions. Best-in-breed or consolidator is a shape, not a quality, and is never scored.

Release-note detail over time

See how much detail Capstone puts in its release notes, quarter by quarter, and compare it with tracked tools in the same category. This history uses up to ten retained, reviewed notes per tool; sparse or blank older quarters may reflect that limit.

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Releases

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32 entries

  1. September 20262
  2. July 20261
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  4. May 20265
  5. February 20261
  6. January 20261
  7. December 20252
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  9. April 20251
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  12. November 20241
  13. September 20241
  14. August 20241
  15. August 20231
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  17. February 20221
  18. May 20201
  19. January 20191
  20. December 20181
  21. July 20171
  22. March 20171
  23. May 20151
  24. November 20141
  25. March 20141
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    32 entries

    Project health

    Issue, contributor and maintainer activity in aquynh/capstone, 2023-10 – 2026-09, as of 2026-09-25. Twelve-month figures first; the trend lines run the whole window.

    1. Contributors 37 +14 vs prior 12 months
    2. Maintainers 6 +4 joined · −3 left, last 12 months
    3. Bus factor 2 committers behind half the commits
    4. Community-filed not measured of issues opened, last 12 months
    5. Median time to close not measured issues closed, last 12 months
    6. Open backlog not measured open issues today
    1. Issues opened / month not measured
    2. Open backlog not measured
    3. Contributors / month 7
    4. Commits / month 22
    5. Stars 9,022
    Issue themes, last 12 months not measured

    Counts from the project's public repository and git history; no individuals are identified. Maintainers are the committers covering 80% of the last year's commits. how we measure this

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